The present invention relates to integrated circuit (semiconductor) devices and methods of forming the same, and more particularly, to a multilevel integrated circuit devices and methods of forming the same.
Many modern electronic appliances include integrated circuit (semiconductor) devices having electronic elements, such as transistors, resistors, and capacitors. The semiconductor devices are generally designed and manufactured to perform predetermined functions associated with operation of the electronic appliances. For example, electronic appliances, such as computers and digital cameras, typically include semiconductor devices, such as a memory chip for storing information and a processing chip for controlling information control, which chips are formed on an integrated circuit (semiconductor) substrate.
To meet consumer expectations of performance and pricing for such electronic appliances, it may be desirable to improve the integration density and the operating speed of the semiconductor devices. To improve the integration density, the electronic elements constituting the semiconductor device generally are formed smaller than with less highly integrated semiconductor devices. As the level of miniaturization in the electronic elements generally depends on the developing speed of a manufacturing technique (especially, photolithography) in a semiconductor device, the development of an advanced processing technique may be desirable in forming the highly integrate the semiconductor devices. The development of advanced process techniques for this purpose is typically costly and long development periods may be required, which limits progress in improving speed in the integration of the semiconductor device.
Techniques have been proposed that arranges semiconductor transistors in a multilevel structure. For example, a NOR flash memory having a multilevel structure is described in Japanese Patent Publication No. 11-145431. When forming the transistors in a multilevel structure, more transistors can generally be formed on an identical area. Therefore, the integration of the semiconductor device may be significantly increased.
As the operating speed of the semiconductor device typically largely depends on a line structure thereof, the resistance of lines in the line structure may need to be reduced to increase the operating speed of the device. However, in the case of a semiconductor device having a multilevel transistor structure, the transistors are generally arranged three-dimensionally, such that a structure of lines connecting the transistors typically becomes more complex. As a result, the resistances of the lines in the line structure typically increases. For example, according to the Japanese Patent Publication No. 11-145431, drain regions of transistors constituting a NOR memory cell array are connected to a bit line through a predetermined select transistor. In this case, as the bit line and the drain region are electrically connected through a channel region of the select transistor, electric resistance increases between the bit line and the drain region. One of the main advantages of the NOR flash memory is typically a fast reading speed, but the increase in electric resistance generally deteriorates quality of the NOR flash memory.
Furthermore, according to the Japanese Patent Publication No. 11-145431, it is difficult to apply a self aligned source (SAS) technique that is generally used in connecting the source regions of the NOR flash memory. More specifically, the SAS technique includes removing device isolation layer patterns to expose a semiconductor substrate in a direction parallel to word lines, and implanting impurities on the exposed semiconductor substrate. An example of the SAS technique is disclosed in Korea Patent Publication No. 10-2003-0100489. In the case of the NOR flash memory of the Japanese Patent Publication No. 11-145431, the semiconductor layers formed on the semiconductor substrate have a thickness identical to the device isolation layer pattern thereof. That is, the device isolation layer pattern passes through the semiconductor layer, such that the semiconductor layer is divided into a plurality of separated regions. Consequently, the separated regions of the semiconductor layer are not connected to each other, and they are not used as common source regions of the NOR flash memory.